1. Technical Field
The embodiments disclosed herein relate to an apparatus for generating pumping voltage, and more particularly, to an apparatus for generating pumping voltage capable of high speed bank actuation for a semiconductor memory apparatus operating in a multi-CS (Chip Select) mode.
2. Related Art
Generally, in a semiconductor memory apparatus, pins are commonly required to operate DRAM devices, wherein a Chip Select (CS) pin determines whether a specific DRAM is operated or not. For example, when the CS pin is enabled at a low level, the DRAM devices are functional, and when the CS pin is at a high level, the DRAM device are not functional regardless of the other input pins.
Currently, for convenience, a semiconductor memory apparatus is provided with two CS pins, thereby the one semiconductor memory apparatus may be used as two semiconductor memory apparatuses. For example, in 1 Gb DRAM device, if two different CS pins control the operations of the 512 Mb cell, the effect is of two 512 Mb DRAMs being used. Here, when two cells that are designed in one DRAM device are operated as an independent DRAM, an actuation interval between the cells is reduced. For example, when a first cell having bank0 and bank1 is controlled by a CS signal ‘CS0’ and a second cell having bank2 and bank3 is controlled by a CS signal ‘CS1’, an actuation interval tRRD between bank0 and bank1 is controlled by the same CS signal ‘CS0’ at about 10 ns. However, it is required that the banks controlled by different CS signals ‘CS1’ are operated as independent banks. Accordingly, an actuation interval tRRD_RR between the banks controlled by different CS signals has a very small value as compared to tRRD, and in general, it is about 1 ns.
As described above, if the bank actuation interval is reduced, a temporary AC level drop of internal power used in the semiconductor memory apparatus is rapidly increased. Moreover, in the case of pumping voltage vpp that requires high current and much time for actuation, the drop amount is increased.
FIG. 1 is a schematic diagram of a conventional apparatus for generating pumping voltage. In FIG. 1, the apparatus provides pumping voltage to the bank n. The apparatus includes a pumping voltage detection unit 101 that receives the pumping voltage vpp and the reference voltage vrefp to output a pumping control signal ‘ppea’ when the pumping voltage is lower than the reference voltage. In addition, the apparatus includes a pumping enable signal generation unit 103 that receives the pumping control signal ‘ppea’ and a bank active signal ‘bankAct<n>’ to output a pumping enable signal ‘pumpEn<n>’ when the bank is actuated, and a pumping unit 105 that pumps voltage to output the pumping voltage response to the pumping enable signal ‘pumpEn<n>’.
FIG. 2 is a timing diagram illustrating an operation of a 1 CS mode of the apparatus of FIG. 1. In FIG. 2, the timing diagram illustrates operation of a single chip select mode 1CSmode of the apparatus for generating pumping voltage shown in FIG. 1.
According to the enabling of the bank active signal ‘bankAct<0>’ in respects to bank0, the pumping voltage vpp is reduced, and if the pumping voltage vpp is lower than the reference voltage vrefp, the pumping control signal ‘ppea’ is enabled. However, in order for the pumping voltage detection unit 101 to detect a voltage level and output it, a predetermined response time is required. Thus, after the pumping voltage vpp becomes lower than the reference voltage vrefp and when a predetermined time t1 is passed, the pumping control signal ‘ppea’ is enabled.
In addition, even after the pumping enable signal ‘pumpEn<0>’ is enabled by the pumping control signal ‘ppea’ and the pumping unit 105 starts to operate, a time t2 until the pumping voltage vpp is boosted is required. Accordingly, after the bank is activated, it takes a time of t1+t2 to boost the pumping voltage.
In the 1CS mode of a semiconductor memory device, since an active interval tRRD between the banks is about 10 ns, according to activation of bank0, after the reduced pumping voltage is boosted, i.e., after t1+t2, the bank active signal ‘bankAct<1>’ with respect to bank1 is enabled, thus the semiconductor memory apparatus is normally operated.
However, in the multi chip select mode 2CS mode of a semiconductor memory device, because the active interval tRRD_RR between the banks controlled by different CS signals is short, the reduction amount of pumping voltage vpp is boosted.
FIG. 3 is a timing diagram illustrating a conventional voltage pumping operation of a 2CS mode semiconductor memory apparatus. In FIG. 3, the timing diagram illustrates a general voltage pumping operation of a 2CS mode semiconductor memory apparatus.
If the bank active signal ‘bankAct0’ with respect to bank0 operated by the CS0 signal is enabled, then the pumping voltage vpp is reduced. Subsequently, if the bank active signal ‘bankAct<2>’ with respect to bank2 operated by the CS1 signal is enabled, the pumping voltage vpp is further reduced. For example, since the actuation interval tRRD_RR between bank0 and bank2 actuated by different CS signals ‘CS0’ and ‘CS1’ is about 1 ns, which is relatively short, in the pumping voltage detection unit, while the pumping control signal ‘ppea’ is output, the pumping voltage vpp is further reduced as compared to the 1CS mode.
In addition, even after the pumping enable signal0 ‘pumpEn<0>’ output by the pumping control signal ‘ppea’ and the bank active signal ‘bankAct<0>’ with respect to bank0, and the pumping enable signal1 ‘pumpEn<1>’ output by the pumping control signal ‘ppea’ and the bank active signal ‘bankAct<2>’ with respect to bank2 are enabled, since a predetermined time is required in pumping, the pumping voltage vpp is continuously reduced. Accordingly, there are problems in that precise data is not recorded in cells and failure occurs.